Secure electronic devices can be designed for use by select users. Unauthorized users who are not permitted to use the secure electronic device are prevented from using the device by logic within the device. However, if the unauthorized users could review the rules that disallow the unauthorized users from using the secure electronic device, the unauthorized users could circumvent the rules and use the device without authorization.
In particular, during thorough testing of the secure electronic devices, it is possible to inadvertently divulge the contents of the secure logic. Despite the possibility of divulging the contents of the secure logic, it is necessary to thoroughly test devices, including the secure logic, before sending them to users.
Referring to FIG. 1, a block diagram of a device 10 is shown. The device 10 has an input 12, an input 14, an output 16 and an output 18. The inputs 12 and 14 and the outputs 16 and 18 can be part of a test access port (TAP) of the device 10. The input 12 is used to input test vectors TDI. The input 14 is used to input a shift enable signal (or instruction) SHFT_EN. The output 16 presents an output of a test instruction serial shift register (or scan chain) 20. The output 18 presents an output TDO of a test result serial shift register (or scan chain) 22.
Logic 24 can be connected between the chain 20 and the chain 22. In one example, the shift input 14 is used to shift in test vectors from the input 12 to the chain 20. The test vectors in the chain 20 may be presented to inputs of the logic 24. The logic 24 may generate outputs in response to the test vectors presented at the inputs. The outputs of the logic 24 may be stored in the chain 22. Contents of the chain 22 may be shifted out via the output 18 in response to the shift enable signal received at the input 14.
Testing of a device using the scan chains is a common test technique to achieve thorough testing of electronic devices. All of the registers in a design are put into a serial chain, so that data can be serially applied to the device. The device is put into a normal mode, the response(s) to the serially applied data collected, and the device put back into the serial mode to shift the response(s) out.
In the device 10, a “11” sequence is loaded into the serial chain 20, and a response of “1” is collected in a register R1 in the serial chain 22. The contents of the chains 20 and 22 are shifted in/out when the signal SHFT_EN is asserted. If the signal SHFT_EN is not asserted, the contents of the register R1 cannot be observed at the chip output 18. In general, for the register R1 to be shifted out to be observed, the contents of registers R2 and R3 also become visible. If the registers R2 and R3 contain secure data, the secure data may be divulged in the process of observing the register R1.
There is a need for thorough testing of secure logic, without divulging any secrets that would allow unauthorized users to use the device.